Freescale Semiconductor /MKL27Z4 /I2S0 /TCR4

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as TCR4

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)FSD 0 (0)FSP 0 (0)ONDEM 0 (0)FSE 0 (0)MF 0SYWD0 (FRSZ)FRSZ 0 (00)FPACK 0 (0)FCONT

FCONT=0, MF=0, FPACK=00, FSD=0, FSP=0, ONDEM=0, FSE=0

Description

SAI Transmit Configuration 4 Register

Fields

FSD

Frame Sync Direction

0 (0): Frame sync is generated externally in Slave mode.

1 (1): Frame sync is generated internally in Master mode.

FSP

Frame Sync Polarity

0 (0): Frame sync is active high.

1 (1): Frame sync is active low.

ONDEM

On Demand Mode

0 (0): Internal frame sync is generated continuously.

1 (1): Internal frame sync is generated when the FIFO warning flag is clear.

FSE

Frame Sync Early

0 (0): Frame sync asserts with the first bit of the frame.

1 (1): Frame sync asserts one bit before the first bit of the frame.

MF

MSB First

0 (0): LSB is transmitted first.

1 (1): MSB is transmitted first.

SYWD

Sync Width

FRSZ

Frame size

FPACK

FIFO Packing Mode

0 (00): FIFO packing is disabled

2 (10): 8-bit FIFO packing is enabled

3 (11): 16-bit FIFO packing is enabled

FCONT

FIFO Continue on Error

0 (0): On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.

1 (1): On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.

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